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FEDS8104160-03
OKI Semiconductor MS8104160
(262,214-word x 8-Bits) x 2 Dual FIFO
REVISION3 2000.9.28
GENERAL DESCRIPTION
The MS8104160 is a single-chip 4Mb FIFO functionally composed of two OKI 2Mb FIFO (First-In First-Out) memories which were designed for 256k x 8-bit high-speed asynchronous read/write operation. The read clocks and the write clocks of each of the 2Mb FIFO memories are connected in common. The MS8104160, functionally compatible with Oki's 2Mb FIFO memory (MSM518222A), can be used as a x16 configuration FIFO. The MS8104160 is a field memory for wide or low end use in general commodity TVs and VTRs exclusively and is not designed for high end use in professional graphics systems, which require long term picture storage, data storage, medical use and other storage systems. The MS8104160 provides independent control clocks to support asynchronous read and write operations. Different clock rates are also supported, which allow alternate data rates between write and read data streams. The MS8104160 provides high speed FIFO (First-in First-out) operation without external refreshing: MS8104160 refreshes its DRAM storage cells automatically, so that it appears fully static to the users. Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic. The MS8104160's function is simple, and similar to a digital delay device whose delay-bitlength is easily set by reset timing. The delay length and the number of read delay clocks between write and read, is determined by externally controlled write and read reset timings. Additional SRAM serial registers, or line buffers for the initial access of 256 x 16-bit enable high speed first-bit-access with no clock delay just after the write or read reset timings. Additionally, the MS8104160 has a write mask function or input enable function (IE), and read- data skipping function or output enable function (OE). The differences between write enable (WE) and input enable (IE), and between read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address increments, but IE and OE cannot stop the increment, when write/read clocking is continuously applied to MS8104160. The input enable (IE) function allows the user to write into selected locations of the memory only, leaving the rest of the memory contents unchanged. This facilitates data processing to display a "picture in picture" on a TV screen.
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FEDS8104160-03 MS8104160 OKI Semiconductor
FEATURES
512 Rows x 512 columns x 8 bits x2 Fast FIFO(First-In First-out)Operation :20ns cycle time self refresh(No refresh control is required) High speed asynchronous serial access Read/write Cycle Time 20ns/25ns/30ns Access Time 18ns/22ns/25ns Variable length delay bit (600 to 262215) Write mask function (Input enable control) Data skipping function (Output enable control) Cascading capability by mode setting Single power supply:5V10% Package : 100-Pin plastic TQFP(TQFP 100-P-1414-0.50-k)(Product:MS8104160XXTB) xx indicates speed rank.
Parameter Access Time Read/Write Cycle Time Operation current Standby current
Symbol tAC tSWC tSRC Icc1 Icc2
EIAA E|
MS8104160-xxTB -20 -25 -30 18ns 22ns 25ns 20ns 170mA 5mA 25ns 150mA 5mA 30ns 120mA 5mA
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FEDS8104160-03 MS8104160 OKI Semiconductor
PIN CONFIGURATION (TOP VIEW)
NC Vss Vss NC OE2 RE2 RSTR2 Vcc NC MODE1 NC Vss NC Vcc NC Vss Vcc Vss WE2 IE2 RSTW2 DI 20 DI 21 DI 22 NC
100
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
NC DI 23 Vss DI 24 DI 25 DI 26 DI 27 NC Vss Vss Vcc Vcc SWCK Vcc Vcc Vss Vss NC DI 17 DI 16 DI 15 DI 14 Vss DI 13 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 PIN TQFP TOP VIEW
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
Vcc DO 20 DO 21 Vss DO 22 DO 23 DO 24 DO 25 Vss DO 26 DO 27 Vcc SRCK Vcc DO 17 DO 16 Vss DO 15 DO 14 DO 13 DO 12 Vss DO 11 DO 10 Vcc
Function Function Pin Name Pin Name Serial Write Clock Serial Read Clock SWCK SRCK Port1 Write Inable Port2 Write Inable WE1 WE2 Port1 Read Inable Port2 Read Inable RE1 RE2 Port1 Input Inable Port2 Input Inable IE1 IE2 Port1 Output Inable Port2 Output Inable OE1 OE2 Port1 Reset Write Port2 Reset Write RSTW1 RSTW2 Port1 Reset Read Port2 Reset Read RSTR1 RSTR2 Port1 Data Input Port2 Data Input DI 10-17 DI 20-27 DO 10-17 Port1 Data Output DO 20-27 Port2 Data Output MODE1,2,3 Mode Input No Connection NC Power Supply(5V) Ground(0V) Vcc Vss
Note: The same power supply voltage must be provided to every Vcc pin,and the same GND voltage level must be provided to every Vss pin.
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50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 NC Vss Vss NC OE1 RE1 RSTR1 Vcc MODE3 MODE2 NC Vss NC Vcc NC Vss Vcc Vss WE1 IE1 RSTW1 DI 10 DI 11 DI 12 NC
MS8104160
DO (G8) SRCK RE2
OE1
RE1
RSTR1
SRCK RSTR2
OE2 DO (G8)
BLOCK DIAGRAM
Data-Out Buffer (G8) Serial Read Controller
Serial
Read
Controller
Data-Out Buffer (G8)
512 Word Serial Read Register (G8) Read Line Buffer High-Half (G8) 256 (G8) 256 (G8) 71 Word Sub-Register (G8) 256k (G8) Memory Array Read Line Buffer Low-Half (G8)
512 Word Serial Read Register (G8) Read Line Buffer Read Line Buffer Low-Half (G8) High-Half (G8) 256 (G8)
256 (G8)
71 Word Sub-Register (G8)
256k (G8)
4
Decoder Decoder Clock Oscillator 256 (G8) 256 (G8) Write Line Buffer High-Half (G8) MODE1,2,3 Serial SWCK VBB Generator SWCK
71 Word Sub-Register (G8)
Memory Array
-
Read/Write and Refresh Controller
Read/Write and Refresh Controller
-
71 Word Sub-Register (G8) 256 (G8) Write Line Buffer Low-Half (G8)
256 (G8)
Write Line Buffer Write Line Buffer High-Half (G8) Low-Half (G8)
512 Word Serial Write Register (G8)
512 Word Serial Write Register (G8)
Data-In Buffer (G8)
Serial
Write
Controller
Write
Controller
Data-In Buffer (G8)
OKI Semiconductor
FEDS8104160-03
DI (G8)
IE1
WE1
RSTW1
RSTW2
WE2
IE2
DI (G8)
FEDS8104160-03 MS8104160 OKI Semiconductor
PIN DESCRIPTION
Data Inputs: (DIN 10 - 17) These pins are used for serial data inputs. Write Reset: RSTW1 The first positive transition of SWCK after RSTW becomes high resets the write address pointers to zero. RSTW1 setup and hold times are referenced to the rising edge of SWCK. Because the write reset function is solely controlled by the SWCK rising edge after the high level of RSTW, the states of WE1 and IE1 are ignored in the write reset cycle. Before RSTW1 may be brought high again for a further reset operation, it must be low for at least two SWCK cycles. Write Enable: WE1 WE1 is used for data write enable/disable control. WE1 high level enables the input, and WE1 lowlevel disables the input and holds the internal write address pointer. There are no WE1 disabletime (low) and WE1 enable time (high) restrictions, because the MS8104160 is in fully static operation as long as the power is on. Note that WE1 setup and hold times are referenced to the rising edge of SWCK. Input Enable: IE1 IE1 is used to enable/disable writing into memory. IE1 high level enables writing. The internal write address pointer is always incremented by cycling SWCK regardless of the IE1 level. Note that IE1 setup and hold times are referenced to the rising edge of SWCK. Data Out: (DOUT 10 - 17) These pins are used for serial data outputs. Read Reset: RSTR1 The first positive transition of SRCK after RSTR1 becomes high resets the read address pointers to zero. RSTR1 setup and hold times are referenced to the rising edge of SRCK. Because the read reset function is solely controlled by the SRCK rising edge after the high level of RSTR, the states of RE1 and OE1 are ignored in the read reset cycle. Before RSTR may be brought high again for a further reset operation, it must be low for at least *two SRCK cycles. Read Enable: RE1 The function of RE1 is to gate of the SRCK clock for incrementing the read pointer. When RE1 is high before the rising edge of SRCK, the read pointer is incremented. When RE1 is low, the read pointer is not incremented. RE1 setup times (tRENS and tRDSS) and RE1 hold times (tRENH and tRDSH) are referenced to the rising edge of the SRCK clock. Output Enable: OE1 OE1 is used to enable/disable the outputs. OE1 high level enables the outputs. The internal read address pointer is always incremented by cycling SRCK regardless of the OE1 level. Note that OE1 setup and hold times are referenced to the rising edge of SRCK.
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FEDS8104160-03 MS8104160 OKI Semiconductor
Serial Write Clock: SWCK The SWCK latches the input data on chip when WE1, 2 is high, and also increments the internal write address pointer. Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK. Serial Read Clock: SRCK Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE1, 2 is highduring a read operation. The SRCK input increments the internal read address pointer when RE1,2 is high. The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of SRCK. *There are no output valid time restriction on MS8104160. Data Input: (DIN 20-27) These pins are used for serial data inputs. Write Reset: RSTW2 The first positive transition of SWCK after RSTW becomes high resets the write address pointers to zero. RSTW2 setup and hold times are referenced to the rising edge of SWCK. Because the write reset function is solely controlled by the SWCK rising edge after the high level of RSTW2, the states of WE2 and IE2 are ignored in the write reset cycle. Before RSTW2 may be brought high again for a further reset operation, it must be low for at least two SWCK cycles. Write Enable: WE2 WE is used for data write enable/disable control. WE2 high level enables the input, and WE2 lowlevel disables the input and holds the internal write address pointer. There are no WE2 disabletime (low) and WE2 enable time (high) restrictions, because the MS8104160 is in fully static operation as long as the power is on. Note that WE2 setup and hold times are referenced to the rising edge of SWCK. Input Enable: IE2 IE2 is used to enable/disable writing into memory. IE2 high level enables writing. The internal write address pointer is always incremented by cycling SWCK regardless of the IE2 level. Note that IE2 setup and hold times are referenced to the rising edge of SWCK. Data Out : DOUT 20 - 27 These pins are used for serial data outputs. Read Reset: RSTR2 The first positive transition of SRCK after RSTR2 becomes high resets the read address pointers to zero. RSTR2 setup and hold times are referenced to the rising edge of SRCK. Because the read reset function is solely controlled by the SRCK rising edge after the high level of RSTR2, the states of RE2 and OE2 are ignored in the read reset cycle. Before RSTR2 may be brought high again for a further reset operation, it must be low for at least *two SRCK cycles.
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FEDS8104160-03 MS8104160 OKI Semiconductor
Output Enable: OE2 OE2 is used to enable/disable the outputs. OE2 high level enables the outputs. The internal read address pointer is always incremented by cycling SRCK regardless of the OE2 level. Note that OE2 setup and hold times are referenced to the rising edge of SRCK. Mode Setting: MODE1 The Cascade/Non cascade select pin. Setting the MODE1 pin to the Vcc level configures this memory device as cascade type and setting the pin to the Vss level configures this memory device as non cascade. During memory operation, the pin must be permanentry connected to Vcc or Vss. If a MODE1 level is changed during memory operation, memory data is not guaranteed. Note: Cascade/Non cascade When MODE1 is set to the Vss level, memory accessing starts in the cycle in which the control signals are input (Non cascade type). When MODE1 is set to the Vcc level, memory accessing starts in the cycle subsequent to the cycle in which the control signals are input (Cascade type). This type is used for consecutive memory accessing. MODE2 Setting: MODE2 MODE2 selects whether the control input signals are enabled at a high level or a low level. Setting MODE2 to the Vcc level enables the control input signals at a low level and setting MODE2 to the Vss level enables the control input signals at a high level. MODE Setting: MODE3 The boost control pin for data-out Buffer. For the MS8104160, the MODE3 pin should be permanently connected to the Vss level. For the MS81V04160, the MODE3 pin should be permanently connected to the Vcc level.
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FEDS8104160-03 MS8104160 OKI Semiconductor
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Input Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT I OS PD T opr Tstg Condition at Ta = 25oC, VSS Ta = 25oC Ta =25oC Rating -1.0 to 7.0 50 1 0 to 70 -55 to 150 Unit V mA

oC oC
W
Recommended Operating Conditions
Parameter Power Supply Voltage Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 -0.3 Typ. 5.0 0 VCC 0 Max. 5.5 0 VCC + 1 0.8 Unit V V V V
DC Characteristics
Parameter Input LeadKage Current Output LeadKage Current Output "H" Level Voltage Output " L" Level Voltage Operating Current Standby Current Symbol ILI ILO VOH VOL ICC1 ICC2A ICC2B Condition
0 < VI< VCC, Other Pins Tested at V=0V 0 < VO< VCC
Min. -10 -10 2.4 -
Max. 10 10 0.4 170 5 15
Unit uA uA V V mA mA
IOH = -1 mA IOL = 2 mA
Minimum Cycle Time, Output Open MODE2="L" MODE2="H"
Input Pin = VIH / VIL
Capacitance
Parameter
(Ta = 25oC , f = 1 MHz)
Symbol CI CO Max. 7 7 Unit pF pF
Input Capacitance (DIN,SWCK,SRCK,RSTW,RSTR,WE,RE,IE,OE) Outnput Capacitance (DOUT)
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FEDS8104160-03 MS8104160 OKI Semiconductor
AC Characteristics
Parameter Access Time from SRCK DOUT Hold Time from SRCK DOUT Enable Time from SRCK SWCK "H" Pulse Width SWCK "L" Pulse Width Input Time Data Setup Input Data Hold Time WE Enable Setup Time WE Enable Hold Time WE Disable Setup Time WE Disable Hold Time IE Enable Setup Time IE Enable Hold Time IE Disable Setup Time IE Disable Hold Time WE "H" Pulse Width WE "L" Pulse Width IE "H" Pulse Width IE "L" Pulse Width RSTW Setup Time RSTW Hold Time SRCK "H" Pulse Width SRCK "L" Pulse Width RE Enable Setup Time RE Enable Hold Time RE Disable Setup Time RE Disable Hold Time OE Enable Setup Time OE Enable Hold Time OE Disable Setup Time OE Disable Hold Time RE "H" Pulse Width RE "L" Pulse Width OE "H" Pulse Width OE "L" Pulse Width RSTR Setup Time RSTR Hold Time SWCK Cycle Time SRCK Cycle Time Transition Time (Rise and Fall) Symbol t AC t DDCK t DECK t WSWH t WSWL t DS t DH t WENS t WENH t WDSS t WDSH t IENS t IENH t IDSS t IDSH t WWEH t WWEL t WIEH t WIEL t RSTWS t RSTWH t WSRH t WSRL t RENS t RENH t RDSS t RDSH t OENS t OENH t ODSS t ODSH t WREH t WREL t WOEH t WOEL t RSTRS t RSTRH t SWC t SRC tT
MS8104160-20
( VAA = 4.5 - 5.5V,Ta = 0 to 70oC )
MS8104160-25 MS8104160-30
Min. 6 6 10 10 3 5 5 (7) 5 5 5 5 (7) 5 5 5 5 5 5 5 3 5 10 10 5 5 5 5 5 5 5 5 5 5 5 5 3 5 20 20 3
Max. 18 18 30
Min. 6 6 12 12 3 5 5 (7) 5 5 5 5 (7) 5 5 5 5 5 5 5 3 10 12 12 5 5 5 5 5 5 5 5 5 5 5 5 3 5 25 25 3
Max. 22 22 30
Min. 6 6 15 15 5 5 5 (7) 5 5 5 5 (7) 5 5 5 10 10 10 10 3 10 15 15 5 5 5 5 5 5 5 5 10 10 10 10 3 10 30 30 3
Max. 25 25 30
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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FEDS8104160-03 MS8104160 OKI Semiconductor
Notes: 1. Input signal reference levels for the parameter measurement are VIH = 3.0 V and VIL = 0 V. The transition time tT is defined to be a transition time that signal transfers between VIH = 3.0 V and VIL = 0 V. 2. AC measurements assume tT = 3 ns. 3. Read address must have more than a 600 address delay than write address in every cycle when asynchronous read/write is performed. 4. Read must have more than a 600 address delay than write in order to read the data written in a current series of write cycles which has been started at last write reset cycle: this is called "new data read". When read has less than a 70 address delay than write, the read data are the data written in a previous series of write cycles which had been written before at last write reset cycle: this is called "old data read". 5. When the read address delay is between more than 71 and less than 599 or more than 262,214, read data will be undetermined. However, normal write is achieved in this address condition. 6. Outputs are measured with a load equivalent to 1 TTL load and 30 pF. Output reference levels are VOH = 1.5 V and VOL = 1.5 V. 7. ( ): MODE2=Vcc
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FEDS8104160-03 MS8104160 OKI Semiconductor
OPERATION MODE
Write Operation Cycle (MODE2=Vss) The write operation is controlled by seven control signals, SWCK, RSTW1, RSTW2, WE1, WE2 and IE1, IE2. Port1 write operation is accomplished by cycling SWCK, and holding WE1 high after the write address pointer reset operation or RSTW1. RSTW1 must be preformed for internal circuit initialization before Write operation. Each write operation, which begins after RSTW1, must contain at least 80 active write cycles, i.e. SWCK cycles while WE1 and IE1 are high. To transfer the last data to the DRAM array, which at that time is stored in the serial data registers attached to the DRAM array, an RSTW1 operation is required after the last SWCK cycle. Note that every write timing of MS8104160 is delayed by one clock compared with read timings for easy cascading without any interface delay devices. Setting MODE1 to the Vss level starts write data accessing in the cycle in which RSTW1, WE1, and IE1 control signals are input. Setting MODE1 to the Vcc level starts write data accessing in the cycle subsequent to the cycle in which RSTW1, WE1, and IE1 control signals are input. These operation are the same for Port1 and Port2.
Settings of WE1, 2 and IE1, 2 to the operation mode of Write address pointer and Data input.
WE1,2 H H L
IE1,2 H L X
Internal Write address pointer Incremented Halted
Data input Input Not input
O aeeaaeana aien aia
Write Operation Cycle (MODE2=Vcc) The write Operation is controlled by seven control signals, SWCK, RSTW1, RSTW2, WE1, WE2, and IE1, IE2. Port1 write operation is accomplished by cycling SWCK and holding both WE1 and IE1 low after the write address pointer reset operation or RSTW1. RSTW1 must be performed for internal circuit initialization before write operation. Each write operation, which begins after RSTW1, must contain at least 80 active write cycle, i.e. SWCK cycles while WE1 and IE1 are high. To transfer the last data to the DRAM array, which at that time is stored in the serial data registers attached to the DRAM array, an RSTW1 operation is required after the last SWCK cycle. Note that every write timing of MS8104160 is delayed by one clock compared with read timings for easy cascading without any interface delay devices. Setting MODE1 to the Vss level starts write data accessing in the cycle in which RSTW1.WE1, and IE1 control signals are input. Setting MODE1 to the Vcc level starts write data accessing in the cycle in which RSTW1, WE1, and IE1 control signals are input. Setting MODE1 to the Vcc level starts write data accessing in the cycle subsequent to the cycle in which RSTW1, WE1, and IE1 control signals are input. These operations are the same for port1 and Port2.
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FEDS8104160-03 MS8104160 OKI Semiconductor
Settings of WE1, 2 and IE1, 2 to the operation mode of Write address pointer and Data input.
WE1,2 L L H
IE1,2 L H X
Internal Write address pointer Incremented Halted
Data input Input Not input
O aeeaaeana aien aia
Read Operation Cycle (MODE2=Vss) The read operation is controlled by seven control signals, SRCK, RSTR1, RSTR2, RE1, RE2, and OE1, OE2. Port1 read operation is accomplished by cycling SRCK, and holding both RE1 and OE1 high after the read address pointer reset operation or RSTR1. Each read operation, which begins after RSTR1, must contain at least 80 active read cycles, i.e. SRCK cycles while RE1 and OE1 are high. These operations are the same for Port1 and Port2. Settings of RE1, 2 and OE1, 2 to the operation mode of read address pointer and Data output.
RE1,2 H H L E
OE1,2 H L H E
Internal Write address pointer Incremented Halted
Data output Output High impedance Ionion Aaeaa aeeiaaeaa
Read Operation Cycle (MODE2=Vcc) The read operation is controlled by four control signals, SRCK, RSTR1, RSTR2, RE1, RE2, and OE1, OE2. Port1 read operation is accomplished by cycling SRCK, and holding both RE1 and OE1 high after the read address pointer reset operation or RSTR1. Each read operation, which begins after RSTR1, must contain at least 80 active read cycles, i.e. SRCK cycles while RE1 and OE1 are low. These operations are the same for Port1 and Port2.
Settings of RE1, 2 and OE1, 2 to the operation mode of read address pointer and Data output.
RE1,2 L L H A
OE1,2 L H L A
Internal Write address pointer Incremented Halted
Data output Output High impedance Ionion Aaeaa aeeiaaeaa
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FEDS8104160-03 MS8104160 OKI Semiconductor
Power-up and Initialization On power-up, the device is designed to begin proper operation after at least 100 us after Vcc has stabilized to a value within the range of recommended operating conditions. After this 100 us stabilization interval, the following initialization sequence must be performed. Because the read and write address pointers are undefined after power-up, a minimum of 80 dummy write operations (SWCK cycles) and read operations (SRCK cycles) must be performed, followed by an RSTW1, 2 operation and an RSTR1, 2 operation, to properly initialize the write and the read address pointer. Dummy write cycles/RSTW1, 2 and dummy read cycles/RSTR1, 2 may occur simultaneously. If these dummy read and write operations start while Vcc and/or the substrate voltage has not stabilized, it is necessary to perform an RSTR1, 2 operation plus a minimum of 80 SRCK cycles plus another RSTR1,2 operation, and an RSTW1,2 operation plus a minimum of 80 SWCK cycles plus another RSTW1,2 operation to properly initialize read and write address pointers. Old/New Data Access There must be a minimum delay of 600 SWCK cycles between writing into memory and reading out from memory. If reading from the first field starts with an RSTR1, 2 operation, before the start of writing the second field (before the next RSTW1, 2 operation), then the data just written will be read out. The start of reading out the first field of data may be delayed past the beginning of writing in the second field of data for as many as 70 SWCK cycles. If the RSTR1, 2 operation for the first field read-out occurs less than 70 SWCK cycles after the RSTW1, 2 operation for the second field write-in, then the internal buffering of the device assures that the first field will still be read out. The first field of data that is read out while the second field of data is written is called "old data". In order to read out "new data", i.e., the second field written in, the delay between an RSTW1, 2 operation and an RSTR1, 2 operation must be at least 600 SRCK cycles. If the delay between RSTW1, 2 and RSTR1, 2 operations is more than 71 but less than 600 cycles, then the data read out will be undetermined. It may be "old data" or "new" data, or a combination of old and new data. Such a timing should be avoided.
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FEDS8104160-03 MS8104160 TIMING WAVEFORM
Write Cycle Timing (Write Reset) : MODE1=Vcc , MODE2=Vss
n cycle 0 cycle 1 cycle 2 cycle V IH SWCK V IL tRSTWS tRSTWH tWSWH tWSWL V IH
OKI Semiconductor
tSWC RSTW 1,2 tDS
V IL tDH V IH
DI 10-17/20-27
n-1
n
0
1
2 V IL V IH
IE 1,2 V IL V IH WE 1,2 V IL
Write Cycle Timing (Write Enable) : MODE1=Vcc , MODE2=Vss
n cycle SWCK tWENH tWDSH tWENS WE 1,2 tWWEL tWDSS VIH VIL Disable cycle Disable cycle n+1 cycle VIH
VIL tWWEH VIH DI 10-17/20-27 n-1 n n+1 VIL VIH IE 1,2 VIL VIH RSTW 1,2 VIL
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FEDS8104160-03 MS8104160 OKI Semiconductor
Write Cycle Timing (Input Enable) : MODE1=Vcc , MODE2=Vss
n cycle n+1 cycle n+2 cycle n+3 cycle VIH SWCK tIENH tWIEL IE 1,2 VIL tWIEH VIH DI 10-17/20-27 n-1 n n+3 VIL tIDSH tIENS tIDSS VIL VIH
VIH WE 1,2 VIL VIH RSTW 1,2 VIL
Write Cycle Timing (Write Reset) : MODE1=Vcc , MODE2=Vcc
n cycle SWCK VIL tRSTWS tRSTWH tWSWH tWSWL VIH RSTW 1,2 tDS DI 10-27/20-27 tDH VIH n-1 n 0 1 2 VIL VIH WE 1,2 VIL VIH IE 1,2 VIL tSWC VIL 0 cycle 1 cycle 2 cycle VIH
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FEDS8104160-03 MS8104160 OKI Semiconductor
Write Cycle Timing (Write Enable) : MODE1=Vcc , MODE2=Vcc
n cycle Disable cycle Disable cycle n+1 cycle V IH SWCK tWENH tWDSH tWDSS tWENS WE 1,2 tWWEL V IL tWWEH DI 10-17/20-27 V IH n-1 n n+1 V IL V IH V IL
V IH IE 1,2 V IL
V IH RSTW1,2 V IL
Write Cycle Timing (Input Enable) : MODE1=Vcc , MODE2=Vcc
n cycle n+1 cycle n+2 cycle n+3 cycle V IH SWCK tIENH tIDSH tIDSS tWIEL V IL tWIEH DI 10-17/20-27 V IH n-1 n n+3 V IL V IH WE 1,2 V IL tIENS V IL
V IH
IE 1,2
V IH RSTW 1,2 VIL
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FEDS8104160-03 MS8104160
Write Cycle Timing (Write Reset) : MODE1=Vss , MODE2=Vss
n cycle SWCK VIL tRSTWS tRSTWH tWSWH tWSWL tSWC RSTW 1,2 VIL tDS tDH VIH DI 10-17/20-27 n 0 1 2 3 VIL VIH 0 cycle 1 cycle 2 cycle VIH
OKI Semiconductor
VIH WE 1,2 VIL VIH IE 1,2 VIL
Write Cycle Timing (Write Enable) : MODE1=Vss , MODE2=Vss
n cycle Disable cycle Disable cycle n+1 cycle VIH SWCK tWENH tWWEL tWDSS WE 1,2 VIL tWWEH VIH DI 10-17/20-27 n n+1 n VIL VIH IE 1,2 VIL tWDSH tWENS VIL VIH
VIH RSTW 1,2 VIL
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FEDS8104160-03 MS8104160 OKI Semiconductor
Write Cycle Timing (Input Enable) : MODE1=Vss , MODE2=Vss
n cycle n+1 cycle n+2 cycle n+3 cycle VIH SWCK tIENH tWIEL IE 1,2 VIL tWIEH VIH DI 10-17/20-27 n n n+3 n+4 VIL tIDSH tIENS tIDSS VIL VIH
VIH WE 1,2 VIL VIH RSTW 1,2 VIL
Write Cycle Timing (Write Reset) : MODE1=Vss , MODE2=Vcc
n cycle n-1 cycle 0 cycle 1 cycle 2 cycle VIH SWCK VIL tRSTWS tRSTWH tWSWH tWSWL VIH RSTW 1,2 tDS DI 10-27/20-27 tDH VIH n-1 n 0 1 2 VIL VIH WE 1,2 VIL VIH IE 1,2 VIL tSWC VIL
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FEDS8104160-03 MS8104160 OKI Semiconductor
Write Cycle Timing (Write Enable) : MODE1=Vss , MODE2=Vcc
n cycle Disable cycle Disable cycle n+1 cycle n+2 cycle VIH SWCK tWENH tWDSH tWDSS tWWEL VIL tWWEH DI 10-17/20-27 VIH n n+1 n+2 VIL tWENS VIH WE 1,2 VIL
VIH IE 1,2 VIL
VIH RSTW1,2 VIL
Write Cycle Timing (Input Enable) : MODE1=Vss , MODE2=Vcc
n cycle n+1 cycle n+2 cycle n+3 cycle VIH SWCK tIENH tIDSH tIDSS IE 1,2 tWIEL VIL tWIEH DI 10-17/20-27 VIH n n+3 n+4 VIL VIH WE 1,2 VIL tIENS VIH VIL
VIH RSTW 1,2 VIL
19
FEDS8104160-03 MS8104160 OKI Semiconductor
Read Cycle Timing (Read Reset) : MODE1=Vcc/Vss , MODE2=Vss
n cycle 0 cycle 1 cycle 2 cycle VIH
SRCK tRSTRS tRSTRH tWSRH tWSRL tSRC RSTR 1,2
VIL
VIH
tAC
tDDCK
VIL
DO 10-17/20-27
VOH n-1 n 0 1 2 VOL
VIH RE 1,2 VIL VIH OE 1,2 VIL
Read Cycle Timing (Read Enable) : MODE1=Vcc/Vss , MODE2=Vss
n cycle Disable cycle Disable cycle n+1 cycle V IH SRCK tRENH tRDSH tRENS tWREL RE 1,2 VIL tWREH DO 10-17/20-27 VOH n-1 n n+1 VOL VIH OE 1,2 VIL VIH RSTR 1,2 VIL tRDSS VIH V IL
20
FEDS8104160-03 MS8104160 OKI Semiconductor
Read Cycle Timing (Output Enable) : MODE1=Vcc/Vss , MODE2=Vss
n cycle SRCK tOENH tWOEL OE 1,2 tWOEH VOH DO 10-17/20-27 n-1 n Hi-Z n+3 VOL VIH RE 1,2 VIL VIH RSTR 1,2 VIL tODSH tODSS tDECK tOENS VIL VIH VIL n+1 cycle n+2 cycle n+3 cycle VIH
Read Cycle Timing (Read Reset) : MODE1=Vcc/Vss , MODE2=Vcc
n cycle 0 cycle 1 cycle 2 cycle VIH SRCK VIL tRSTRS RSTR 1,2 tAC tRSTRH tWSRH tWSRL VIH tSRC tDECK VIL VOH DO 10-17/20-27 n-1 n 0 1 2 VOL VIH VIL VIH VIL
RE 1,2
OE 1,2
21
FEDS8104160-03 MS8104160 OKI Semiconductor
Read Cycle Timing (Read Enable) : MODE1=Vcc/Vss , MODE2=Vcc
n cycle Disable cycle Disable cycle n+1 cycle VIH SRCK tRENH tRDSH tRDSS tRENS RE 1,2 tAC tWREH DO 10-17/20-27 VOH n-1 n n+1 VOL VIH OE 1,2 VIL VIH RSTR 1,2 V IL tWREL VIL VIH VIL
Read Cycle Timing (Output Enable) : MODE1=Vcc/Vss , MODE2=Vcc
n cycle n+1 cycle n+2 cycle n+3 cycle VIH SRCK tOENH tODSH tODSS tOENS OE 1,2 tWOEL tWOEH VOH DO 10-17/20-27 n-1 n Hi-Z n+3 VOL VIH RE 1,2 VIL VIH RSTR 1,2 VIL VIH VIL
VIL
22

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